This application claims priority to British Patent Application No. 0104333.0 filed on Feb. 22, 2001.
The present invention relates to semiconductor-on-insulator structures and more particularly, though not necessarily, to silicon-on-insulator structures and to a method of fabricating isolation trenches within such structures.
So called silicon-on-insulator (SOI) structures are known to provide improved performance and reduced power consumption for silicon based electrical devices, due to the electrical isolation of the substrate provided by the underlying oxide insulator. SOI structures may take advantage of trench device isolation in VLSI integrated circuits in order to improve device packing density. FIG. 1 illustrates such an SOI structure comprising a base silicon layer 1, a buried silicon dioxide layer 2, and a silicon substrate 3 in which electrical devices are formed. The substrate layer 3 may comprise several sub-layers (doped and undoped) and/or doped and undoped regions. Trenches 4 are etched through the substrate 3 to the buried oxide layer 2 to isolate the central region of the substrate in the horizontal plane. The walls of the trenches 4 and the surface of the substrate 3 are coated with a thin oxide layer 6 which is used for further processing of the structure. The trenches themselves are lined with dielectric silicon dioxide/silicon nitride layers and filled with polysilicon 5.
With standard silicon structures, trench processing typically involves an oxide masking layer which is chemically removed (using a wet etch) after the trench has been etched. With SOI structures however, the use of an oxide mask and its subsequent removal may cause damage to the buried oxide layer exposed by the trenchxe2x80x94even the use of a temporary plug to fill the trench prior to wet etching does not completely avoid damage to the buried oxide layer as the wet etch tends to xe2x80x9cwickxe2x80x9d down the sides of the plug. The problem is compounded when a surface oxide layer of well defined thickness is required.
A method of fabricating such a device is described in U.S. Pat. No. 5,811,315. A first step is to deposit a hard mask (oxide-nitride-oxide) onto the surface of the substrate 3. The mask is patterned with photoresist, and etched to expose the surface of the substrate 3 where the trenches 4 are to be formed. The trenches 4 are then etched. A layer of sacrificial oxide is then grown on the sidewalls of the trenches and subsequently removed to remove damage to the sidewalls caused by the etching of the trench. A layer of trench lining oxide is grown, and the exposed surfaces coated with silicon nitride. The nitride is selectively removed to leave only the coatings on the trench and hard mask sidewalls. Polysilicon is then deposited to fill the trenches 4, and etched back to expose the hard mask. The upper oxide and nitride layers of the hard mask are removed, leaving only the lower oxide layer of the hard mask. It is noted that the nitride coating on the exposed sidewalls of the lower oxide layer protects the oxide layer from under etching when the upper oxide layer is removed.
The method of U.S. Pat. No. 5,811,315 is complex insofar as it requires a large number of processing steps. This results in part from the need to protect sensitive regions when performing the removal of the upper oxide layer of the hard mask.
According to a first aspect of the present invention there is provided a method of forming an electrical isolation trench in a semiconductor-on-insulator structure, the method comprising:
forming a first oxide layer on top of the upper silicon layer of the semiconductor-on-insulator structure;
forming a polysilicon layer on top of said oxide layer;
forming a second oxide layer on top of said polysilicon layer;
patterning the first oxide layer, polysilicon layer, and second oxide layer to provide an etch mask;
etching the upper semiconductor layer of the semiconductor-on-insulator structure to form said trench;
filling the trench with a temporary plug;
removing said second oxide layer;
removing said polysilicon layer;
removing said temporary plug either before or after removing the polysilicon layer; and
filling the trench with dielectric material.
Preferably, the semiconductor-on-insulator structure is a silicon-on-insulator structure.
Preferably, the method comprises the following steps, subsequent to said step of etching the upper silicon layer of the semiconductor-on-insulator structure to form said trench but prior to said step of removing said second oxide layer and said polysilicon layer:
forming an oxide layer on the sidewalls of the trench; and
filling the trench with resist.
An advantage of forming a polysilicon layer beneath the second oxide layer is that, because the selectivity of oxide to polysilicon for an oxide plasma dry etch is relatively high, the second oxide layer can be removed using a dry etch with the polysilicon providing an etch stop. If a nitride layer is used instead of polysilicon (as proposed in the prior art), the nitride would be etched by the oxide plasma etch.
Following removal of the second oxide layer, the protective resist is removed from the trench. The polysilicon layer is then removed with a wet etch. As the polysilicon to oxide selectivity of the polysilicon wet etch is high, the oxide beneath the polysilicon will be relatively undamaged.
Preferably, said trench extends through the upper silicon layer of the semiconductor-on-insulator structure to a buried oxide layer of the structure.
Preferably, following removal of said second oxide layer and said polysilicon layer, a nitride layer is formed on the exposed surfaces. The trench may then be filled with polysilicon.
Preferably, said first oxide layer is grown on the upper semiconductor layer of the semiconductor-on-insulator structure, whilst the polysilicon and second oxide layers are formed by deposition.
According to a second aspect of the present invention there is provided a semiconductor-on-insulator structure having at least one trench formed therein using the method of the above first aspect of the present invention.
According to a third aspect of the present invention there is provided a method of forming an electrical isolation trench in a semiconductor-on-insulator structure, the method comprising:
forming a first oxide layer on top of the upper semiconductor layer of the semiconductor-on-insulator structure;
forming one or more mask layers on top of said first oxide layer;
patterning the first oxide layer and the one or more mask layers to provide an etch mask;
etching the upper semiconductor layer of the semiconductor-on-insulator structure to form said trench;
filling the trench with resist; and
removing said one or more mask layers.
Preferably, the method comprises forming at least two mask layers on top of said first oxide layer, and removing the resist from the trench subsequent to removing a first of the mask layers but prior to removing a second of the mask layers.